As modern integrated circuit technology becomes more complex, individual circuits have more devices than did prior art circuits, and the devices in the circuits have smaller dimensions than did prior art devices. The goal of more and smaller devices in integrated circuits introduces additional processing and structural complexity as the goal can not be attained by simply scaling down feature size or increasing chip size. For example, the devices, e.g., field effect transistors, must be electrically contacted, and it is difficult to make all electrical interconnections on a single level because of geometrical constraints. Many integrated circuits therefore now have electrical interconnections on two or more levels. Forming the electrical interconnections is simplified if the dielectric layers used to separate different layers of metallization have planar surfaces. However, planar surfaces are frequently difficult to produce because of the complexity of the underlying topography.
Accordingly, methods have been developed for producing planar dielectric surfaces, but these methods are not completely satisfactory in all circumstances. For example, the dielectric can be deposited on the substrate and then a resist can be deposited on the dielectric surface. The resist has a planar surface as deposited and an etchback that removes both resist and dielectric at the same rate will leave a planar dielectric surface when all resist is removed. However, resists are likely to introduce sodium contamination into the dielectric which is undesirable. Alternatively, the deposited dielectric may also be heated to a temperature at which it flows, thereby at least reducing surface height variations.
A commonly used dielectric in integrated circuit fabrication is silicon dioxide produced by a method that uses silane as a precursor gas. The flow temperature of the silicon dioxide can be significantly reduced by the addition of relatively minor amounts of dopants such as boron or phosphorous. The reduction in flow temperature is generally proportional to the concentration of dopants, i.e., a higher dopant concentration produces a greater reduction in flow temperature than does a smaller concentration. Of course, some dopants are more effective in reducing flow temperature than are other dopants. Relatively low flow temperatures are desirable because they minimize adverse effects such as, e.g., n- and p-type dopant diffusion, that elevated temperatures can produce. However, the results produced by flowing the dielectric are generally not perfect, especially for high dopant concentrations.
Some of the problems associated with the planarization techniques described, particularly over closely spaced features such as runners, could be alleviated by the deposition of conformal dielectrics. For example, layers of conformal dielectrics, such as TEOS and BPTEOS, could be sequentially deposited until a planar surface is produced, i.e., until the space between features is substantially filled. However, it has been found that for some conditions, particularly for those dielectrics with relatively high dopant concentrations, the deposition process is not conformal but rather produces a dielectric surface having re-entrant angles. The re-entrant angle is the angle between the vertical surface and the largest tangent to the dielectric surface and it should be small. Large re-entrant angles are undesirable because they can prevent surface planarization from occurring in the flow process. Additionally, high dopant concentrations may decrease film stability.
Techniques that eliminate or reduce the magnitude of the re-entrant angles or which reduce the dopant concentration in the deposited dielectric layer would be desirable.